# Flip-Flop Flip-flop is a sequential logical circuit, which is an edge trigger or sensitive. The flip-flop and latch are made via different logic gates. Flip-flop is different from latch because the clock feature is not present in latches, which is important for Flip-flop operations. The output of Flip-flops will change either at the increasing edge or decreasing edge of the clock pulse, whereas the output is a change in the latch at the change of the level of clock pulse either high or low level.

The block diagram of a standard flip-flop is shown below

A sequential circuit that has only two states, 1 or 0, is called a flip-flop. Its two outputs are complementary to each other.

## Types of Flip-flops

Basically flip-flops are 4 types. These are-

• S-R FF
• D FF
• J-K FF
• T FF

### ﻿Set-Reset or S-R FF:

• The S-R FF is a first and basic FF, which has two inputs – S and R.
• S stands for “Set” and R stands for “Reset”.
• The input of FF is called SET if its output Q has a high value or ‘1’ state, and when it is called RESET, if output Q has a low value or ‘0’ state.
• Both the outputs are the complement of each other (i.e., output Q′ and Q ). Its output depends on the present as well as the previously stored output.
• The characteristic equation is
• The internal circuit and the excitation table of the S-R FF is shown below

#### Input Conditions

1. S =R= 0 is the normal resting or no change condition of the FF. In this condition, the output ports (Q and Q’) hold the previous states, either 0 or 1.
2. S = 0 and R = 1 is the resets or clears state of the FF. It is because RESET has a high or ‘1’ state.
3. S =1 and R =0 is the set state of the FF. It is because SET has a high or ‘1’ state.
4. S = R = 1 is forbidden state of the FF. It is because both the input has a high or ‘1’ state at the same time.

### Delay or D-FF:

• The S-R Flip Flop is a forbidden state. To remove this condition from the FF, connect the input terminal of SR flip-flop with each other via an inverter or NOT gate.
• The internal structure of D FF is shown below. The inverter or NOT gate placed for ensuring that inputs S and R will never equal.
• The structure of D-FF is the same as S-R FF except for a single input terminal.
• There are D stands for ‘Delay” because the inverter produces a small delay between both the input of FF that is directly shown in outputs.
• The characteristic equation is Qn+1 = D

### J-K FF:

• The forbidden state output of S-R FF is removed in D FF, by joining both the inputs via an inverter or NOT gate. But the D FF has a single input terminal.
• The J-K FF is similar to S-R FF because it has 2 inputs i.e., J and K.
• The characteristic equation is
• Both the inputs of J-K FF are high or ‘1’, the output toggles and the forbidden or ambiguous state are removed.

### Toggle or T-FF:

• The two input terminal of J-K flip-flop is connected to each other a new flip-flop is formed, which is called T Flip-flop.
• T stands for “Toggle”.
• The input of T flip-flop is high or ‘1’, the output toggles. This condition is called a toggle mode.
• The input of T flip-flop is low or ‘0’, the output hold. This condition is called hold mode.
• The characteristic equation is